Wow, years after RISC did it, AMD is bringing SIMD to the x86 architecture. They announced their "SSE5"; called extention to the x86 architecture.

Until now, the x86 platform had the major drawback of having a maximum of only two operands in their instructions. The G4 CPUs have an extention called "Altivec"; which is comparable to SSE5 (and has been there for years).

To quote arstechnica:

In a nutshell, a third operand lets a programmer or compiler specify a filter/mod register that can affect the way that a vector operation is carried out on the operands in the other two registers. Such operands are extremely useful for doing in a single instruction a variety of operations that would normally take a sequence of multiple instructions. The use of a third operand register can significantly increase performance for some types of codes, especially in hand-tuned code.

A little information: SIMD means "Single Instruction Multiple Data";

Here is SSE5 in comparison to "other"; SSEs

SSE5 and others

The official PDF

The official developer Page

An article describing SIMD and the x86 shortcomings

A Forum thread dealing with it

via arstechnica